In recent years, speed and functionality of semiconductor chips (IC (Integrated Circuit) chips) used as microprocessors of computers, cellular phones, and the like have been enhanced more and more. Accordingly, there has been a tendency to increase the number of terminals, thereby narrowing a pitch between terminals. Typically, a large number of terminal sections are disposed in an array on a bottom surface of an IC chip.
Since there is a large difference in pitch between the terminal sections in such an IC chip and connection terminals formed on a circuit board called “motherboard”, it is difficult to mount the IC chip on the motherboard.
Therefore, to connect the IC chip to the motherboard, a structure called “semiconductor package” that includes a wiring substrate, and the IC chip and the like mounted on the wiring substrate is formed, and the wiring substrate is mounted on (connected to) the motherboard. Thus, the IC chip is connected to the motherboard through the wiring substrate.
Examples of the above-described wiring substrate may include a so-called coreless type wiring substrate that is configured of a laminate formed by laminating a plurality of insulating layers and a plurality of wiring layers by a buildup method, and does not include a core layer (a core substrate) (for example, refer to the above-described PTLs 1 and 2). Since such a coreless type wiring substrate does not include the core substrate, an entire wiring length in the careless type wiring substrate is reduced to reduce transmission loss of a high-frequency signal. Accordingly, the IC chip is allowed to operate at high speed.
In the above-described wiring substrate, respective wiring layers are connected to one another through respective vias, and a plurality of lands connected to the via are provided to each of the wiring layers.
In the above-described semiconductor package, further downsizing and further enhancement of operation speed and density are desired, and a reduction in parasitic inductance and enhancement of accuracy of control on impedance of a signal line are desired accordingly.
Under present circumstances, impedance control is performed in a same wiring layer of the wiring substrate. The impedance control in this case is executed by a stripline or a microstripline.
In a case where a transmission signal frequency is further increased, and, for example, a signal of 10 GHz or over is transmitted from a semiconductor package to a motherboard, by an influence of impedance, transmission is most limited in a BGA (Ball Grid Array) section other than the wiring layer of the wiring substrate.
Under present circumstances, the transmission signal frequency is not increased to about 10 GHz; therefore, impedance control on the BGA section is not considered important.
As a configuration enabling impedance control on the BGA section, for example, the above-described PTL 3 discloses a configuration in which a spacer sheet with PTHs (plated through holes) is sandwiched between a BGA surface and the motherboard (refer to FIGS. 4, 5, and the like in PTL 3). In each of the PTHs, a copper wiring is formed to cover a periphery of a solder ball in the BGA section, and use of the copper wiring enables impedance control on the BGA section.